Markets for computers, video games, televisions, portable telephones, PDAs and other electrical devices are requiring increasingly larger amounts of memory to store images, photographs, videos, movies, music, and other storage-intensive data. At the same time, as computer and other electrical equipment prices continue to drop, the manufacturers of storage devices, such as memory devices and hard drives, need to lower the cost of their components. Thus, in addition to the need to increase the storage density of their devices, manufacturers of storage devices must also reduce costs. This trend of increasing memory storage density while reducing the fabrication costs of the storage has been on-going for many years. There is accordingly a need for economical, high capacity memory structures and economical methods for fabricating such structures, especially methods that are compatible with methods used to fabricate other elements of integrated circuits.
Integrated circuits including arrays of memory nodes or logic gates have also increased steadily in density. Such integrated circuits have included dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, programmable read-only memory (PROM) integrated circuits, electrically erasable programmable read-only memory (EEPROM) integrated circuits, write-once read-many (WORM) memory devices, and logic devices such as programmable logic array (PLA) integrated circuits, among others.
For controlling write and read operations of multi-layer memory arrays, a control element is generally associated with each memory cell of the array. In many cases, such control elements have required excessive power and have limited array performance. In some cases, the driver circuits for such control elements have required relatively large areas, accounting for about half of the array size.
Tunnel-junction control elements using selected area ratios have required smaller areas, but have required additional mask steps for their fabrication, and have suffered yield losses due to mismatches of tunnel junctions, thus increasing costs.
When the sense lines within a memory array are each connected to a selected memory cell and to many other unselected memory cells, and the unselected memory cells are also connected to unselected bit lines, the many parallel paths through the unselected memory cells from a sense line to the unselected bit lines are generally referred to as “sneak paths.” Thus, currents that flow through the sneak paths (i.e., “sneak-path currents”) have occurred in some arrays, adversely affecting the performance of read operations.
Three-terminal memory cell devices, having a gate electrode for controlling the state of the memory cell, are known. Many of these are “flash” devices, which utilize current injection into floating gates. In a typical flash memory, each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge, and the data stored in a cell is determined by the presence or absence of the charge in the floating gate. Other three-terminal memory cell devices employ Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structures or Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structures in which a gate insulating layer between a channel region and a control gate includes a laminated portion consisting of a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer, and in which the silicon nitride layer traps electric charges. While these memory devices perform their intended functions, there is an on-going need for economical high-yield methods for fabricating memory structures, including memory arrays, especially memory arrays with reduced susceptibility to sneak-path currents.